1. Field of Invention
The present invention relates generally to the field of diagnostic test circuitry for high-speed serial links.
2. Description of Related Art
In telecommunications, an eye pattern is a display on an oscilloscope in which a pseudorandom digital data signal is repetitively sampled and applied to the vertical input of the oscilloscope, while the data rate is used to trigger the horizontal sweep. The eye pattern is so called because when the signal sampled is in NRZ (Non-Return-To-Zero) code, the pattern resembles eyes between a pair of rails. Since a receive waveform can be degraded during transmission due to intersymbol interference, jitter, crosstalk, noise and the like, system performance can be derived by analyzing the eye pattern. An open eye pattern corresponds to minimal signal distortion, while a closed eye pattern implies distortion.
Diagnostic circuits to derive an eye pattern for display on an oscilloscope or monitor are known in the art. In a high-speed serial link receiver, a receive equalizer functions to reduce received signal distortion. At the output of the receive equalizer is an eye pattern detection circuit. However, in the art such eye pattern detection circuits are not located in the same chip as the receive equalizer but are off-chip.
Having the eye pattern detection circuit off-chip has disadvantages. Driving the receive equalizer output signal off-chip requires additional pins on the chip housing the receive equalizer. Driving the signal off-chip also often results in the signal being measured being degraded.
In prior eye pattern detectors, a system of clock interpolation and two additional capture latches is used. The clock is skewed on one capture latch and compared to the other latch to determine the width of the receive eye opening from the output of the receive equalizer. However, the system of clock interpolation and the two additional capture latches add too much extra loading to the equalizer output, as well as requiring two full phase interpolators, one for each latch, to control the clocks. This requires additional cost and power consumption to the receiver circuit being tested.
What is lacking in the prior art is a method and apparatus for a diagnostic circuit for measuring the eye pattern downstream from the output of a receive equalizer in a high-speed receiver serial link, that is on-chip to the circuit housing the receive equalizer, and employs a minimum of capture latches, such as taught in the present invention.